Integrated circuit memory devices may contain both local and global input/output lines for writing and reading data to and from memory arrays therein in an efficient manner. These integrated circuit memory devices may also include conventional merged data test circuits for verifying operability of memory cells in the memory arrays. For example, FIG. 1 is block schematic of a conventional integrated circuit memory device 101 having a plurality of local input/output lines and a plurality of global input/output lines and FIG. 2 is an electrical schematic of a conventional merged data test circuit having inputs electrically connected to the global input/output lines of FIG. 1. For sake of clarity, the local and global input/output lines for transferring complementary data have been omitted from FIG. 1.
In particular, FIG. 1 illustrates a plurality of spaced blocks of memory 111-118 with each block containing a plurality of sub-word line driver circuits 171 and a plurality of memory cell arrays 175, arranged side-by-side as illustrated. As will be understood by those skilled in the art, data can be transferred between local input/output lines 121-124 and the memory cell arrays 175 in the first block of memory 111. Similarly, data can be transferred between local input/output lines 123-126 and the second block of memory 112, between local input/output lines 125-128 and the third block of memory 113, between local input/output lines 127-130 and the fourth block of memory 114, between local input/output lines 129-132 and the fifth block of memory 115, between local input/output lines 131-134 and the sixth block of memory 116, between local input/output lines 133-136 and the seventh block of memory 117, and between local input/output lines 135-138 and the eighth block of memory 118. Global input/output lines 141-156 are also provided so that data can be transferred to and from the local input/output lines and external data pins, for example.
During merged data testing of the first block of memory 111, global input/output lines 141-144 can be electrically connected to local input/output lines 121-124, as illustrated by the dotted connections. Similarly, during merged data testing of the second block of memory 112, global input/output lines 143-146 can be electrically connected to local input/output lines 123-126. Likewise, merged data testing of the third block of memory 113 requires the formation of electrical connections between global input/output lines 145-148 and local input/output lines 125-128, merged data testing of the fourth block of memory 114 requires the formation of electrical connections between global input/output lines 147-150 and local input/output lines 127-130, merged data testing of the fifth block of memory 115 requires the formation of electrical connections between global input/output lines 149-152 and local input/output lines 129-132, merged data testing of the sixth block of memory 116 requires the formation of electrical connections between global input/output lines 151-154 and local input/output lines 131-134, merged data testing of the seventh block of memory 117 requires the formation of electrical connections between global input/output lines 153-156 and local input/output lines 133-136 and merged data testing of the eighth block of memory 118 requires the formation of electrical connections between global input/output lines 155-156 and 141-142 and local input/output lines 135-138.
Referring now to FIG. 2, an electrical schematic of a conventional merged data test circuit is illustrated. This test circuit has inputs electrically connected to the global input/output lines 141-156 of FIG. 1 and outputs electrically connected to test pads 219, 229, 239, 249, 259, 269, 279 and 289. The test circuit also has a plurality of test cells 211, 221, 231, 241, 251, 261, 271 and 281 and each test cell includes a 4-input NOR gate 213, a 4-input AND gate 215 and a 2-input OR gate 217. As will be understood by those skilled in the art, the output of the first test cell 211 will be set to a logic 1 potential whenever global input/output lines 141-144 are all set to logic 0 potentials or all set to logic 1 potentials. Accordingly, the memory cell arrays 175 in the eight blocks of memory 111-118 in FIG. 1 can be individually tested by writing all logic 1 or all logic 0 data into the memory cell arrays 175 and then reading back the written test data via the test circuit. For example, with respect to a memory cell array 175 in the first block 111, data from selected memory cells within four columns of cells may be read onto the first, second, third and fourth local input/output lines 121-124 and then transferred via the first, second, third and fourth global input/output lines 141-144 to the inputs of the first test cell 211. If the first test cell 211 outputs a logic 1 signal to the first test pad 219, then the selected memory cells are functioning correctly with respect to the stored logic 1 or logic 0 data. Similar operations are also performed to test the other memory cell arrays within the other blocks. Thus, with respect to a memory cell array 175 in the second block 112, data from selected memory cells within four columns of cells may be read onto the third, fourth, fifth and sixth local input/output lines 123-126 and then transferred via the third, fourth, fifth and sixth global input/output lines 143-146 to the inputs of the second test cell 221. Based on this configuration, one test cell is required for each block of memory to be tested.
Notwithstanding the above-described integrated circuit memory device having merged data test capability, there continues to be a need for more highly integrated memory devices having improved merged data test circuits therein which are smaller and consume less power.